There are various types of ADC architectures, one of which is the Flash ADC. These are sometimes known as parallel ADCs. They are considered the fastest way to convert an analog signal to a digital signal. They are suitable for applications requiring very large bandwidths. However, Flash converters consume a lot of power, have relatively low resolution, and can be quite expensive. This limits them to high frequency applications that typically cannot be addressed any other way. Examples of conventional use of Flash ADCs include data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disc drives.
A typical ADC includes a plurality of comparators, there being 2N−1 comparators. A resistive divider with 2N resistors provides the reference voltage. The reference voltage for each comparator is at least one least significant bit (LSB) greater than the reference voltage for the comparator immediately below it. Each comparator produces a “1” when its analog input voltage is higher than the reference voltage applied to it. Otherwise, the comparator output is “0.” Thus, if the analog input is between the threshold voltage associated with two adjacent comparators, then the lowest most one of those comparators will output a “1” and all of the lower comparators will also output “1.” The point where the code changes from ones to zeros is the point where the input signal becomes smaller than the respective comparator reference voltage levels. This is known as thermometer code encoding, so named because it is similar to a mercury thermometer, where the mercury column always rises to the appropriate temperature and no mercury is present above that temperature. The thermometer code is then decoded to the appropriate digital output code.
The comparators utilized in the Flash ADC are typically a cascade of wideband low gain stages. They are low gain because of high frequencies. It is difficult to obtain both wide bandwidth and high gain. They are designed for low voltage offset, such that the input offset of each comparator is smaller than an LSB of the ADC. Otherwise, the offset of the comparator could falsely trip the comparator, resulting in a digital output code not representative of a thermometer code. A regenerative latch at each comparator typically stores the result. If this latch has positive feedback, such that the end state is forced to either a “1” or a “0.” In general, there are a number of trade-offs for the various architectures. For Flash converters, the conversion time does not change materially with increased resolution. For successive approximation register ADCs (SAR) or pipelined Converters, this increases approximately linearly with an increase in resolution. For integrating ADCs, the conversion time doubles with every bit increase in resolution. The component matching for Flash ADCs typically limits resolution to around 8-bits. Calibration and trimming are sometimes used to improve the matching available on a chip. Component matching requirements double with every bit increase in resolution. This applies to Flash and SAR converters, but not integrating converters. For integrating converters, component matching does not materially increase with an increase in resolution. For Flash converters, every bit increase in resolution almost doubles the size of the ADC core circuitry. The power also doubles. In contrast, a SAR, pipelined or sigma-delta ADC die size will increase linearly with an increase in resolution, and an integrating converter core die size will not materially change with an increase in resolution. An increase in die size increases cost.
As compared to a SAR ADC, the Flash ADC is more expensive. In a SAR converter, the bits are decided by a single high-speed, high-accuracy comparator one bit at a time (from the MSB down to the LSB), by comparing the analog input with a DAC whose output is updated by previously decided bits and thus successively approximates the analog input. This serial nature of the SAR limits its speed to no more than a few Msps, while Flash ADCs exceed giga-sample per second (Gsps) conversion rates. The SAR converters also typically have higher resolutions than Flash ADCs with a much lower power.
With respect to pipelined ADCs, the pipelined ADC employs a parallel structure in which each stage works on one to a few bits of successive samples concurrently. This improves speed at the expense of power and latency. However, each pipelined stage is much slower than a Flash section. A pipelined ADC requires an accurate amplification in the DACs and interstage amplifiers, and these stages have to settle to a desired linearity level. By contrast, in a Flash ADC, the comparator only needs to be low offset and be able to resolve its inputs to a digital level (i.e., there is no linear settling time involved). However, some Flash converters require a pre-amplifier to drive the comparators. Gain linearity needs to be carefully specified in this type of ADC.
With respect to the integrated ADCs, these type of ADCs can achieve high resolutions and are relatively inexpensive and dissipate materially less power than a Flash ADC. Sigma-delta ADCs typically exceed a Flash ADC in that they achieve conversion rates up to 2 MHz with better resolution, such that they are more suitable for applications with much lower bandwidths, typically less than 1 MHz.